RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design by Stuart Sutherland, ISBN-13: 978-1546776345
[PDF eBook eTextbook]
- Publisher: CreateSpace Independent Publishing Platform; 1st edition (June 10, 2017)
- Language: English
- 488 pages
- ISBN-10: 1546776346
- ISBN-13: 978-1546776345
This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices.SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. The creator of the original Verilog Language, Phil Moorby says about this book (an excerpt from the book’s Foreword): “Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe not even refer to the old ways at all! If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog.”
Table of Contents:
Table of Contents……………………………………………………………………………………………..ix
List of Examples…………………………………………………………………………………………….xvii
List of Figures………………………………………………………………………………………………….xxi
Foreword………………………………………………………………………………………………………..xxv
Preface………………………………………………………………………………………………………….xxvii
Why this book…………………………………………………………………………………………………………xxvii
Intended audience for this book………………………………………………………………………………..xxviii
Topics covered in this book……………………………………………………………………………………..xxviii
Book examples…………………………………………………………………………………………………………xxix
Obtaining copies of the examples………………………………………………………………………………..xxx
Simulators and synthesis compilers used in this book…………………………………………………….xxx
Other sources of information……………………………………………………………………………………..xxxi
Acknowledgements…………………………………………………………………………………………………..xxxi
Chapter 1: SystemVerilog Simulation and Synthesis………………………………………..1
1.1 Verilog and SystemVerilog — a brief history…………………………………………………………1
1.1.1 The Original Verilog………………………………………………………………………………..2
1.1.2 Open Verilog and VHDL………………………………………………………………………….3
1.1.3 IEEE Verilog-95 and Verilog-2001……………………………………………………………3
1.1.4 SystemVerilog extensions to Verilog — a separate standard…………………………4
1.1.5 SystemVerilog replaces Verilog………………………………………………………………..5
1.2 RTL and gate-level modeling……………………………………………………………………………….6
1.2.1 Abstraction……………………………………………………………………………………………..6
1.2.2 Gate-level models…………………………………………………………………………………….7
1.2.3 RTL models…………………………………………………………………………………………..10
1.2.4 Behavioral and transaction-level models…………………………………………………….11
1.3 Defining an RTL synthesis subset of SystemVerilog …………………………………………….12
1.4 Modeling for ASICs and FPGAs…………………………………………………………………………12
1.4.1 Standard cell ASICs……………………………………………………………………………….12
1.4.2 FPGAs…………………………………………………………………………………………………..15
1.4.3 RTL coding styles for ASICs and FPGAs…………………………………………………..16
1.5 SystemVerilog simulation …………………………………………………………………………………..17
1.5.1 SystemVerilog simulators……………………………………………………………………….21
1.5.2 Compilation and elaboration…………………………………………………………………….21
1.5.3 Simulation time and event scheduling……………………………………………………….23
X RTL Modeling with SystemVerilog for Simulation and Synthesis
1.6 Digital synthesis ……………………………………………………………………………………………….31
1.6.1 SystemVerilog synthesis compilers………………………………………………………….32
1.6.2 Synthesis Compilation……………………………………………………………………………33
1.6.3 Constraints……………………………………………………………………………………………34
1.7 SystemVerilog lint checkers……………………………………………………………………………….35
1.8 Logic Equivalence Checkers ………………………………………………………………………………36
1.9 Summary …………………………………………………………………………………………………………37
Chapter 2: RTL Modeling Fundamentals……………………………………………………….39
2.1 Modules and procedural blocks……………………………………………………………………………39
2.2 SystemVerilog language rules…………………………………………………………………………….40
2.2.1 Comments…………………………………………………………………………………………….40
2.2.2 White space…………………………………………………………………………………………..43
2.2.3 Reserved keywords………………………………………………………………………………..44
2.2.4 Keyword backward compatibility — ‘begin_keywords………………………………46
2.2.5 Identifiers (user-defined names)………………………………………………………………49
2.2.6 Naming conventions and guidelines…………………………………………………………50
2.2.7 System tasks and functions……………………………………………………………………..51
2.2.8 Compiler directives………………………………………………………………………………..52
2.3 Modules…………………………………………………………………………………………………………..52
2.4 Modules instances and hierarchy ………………………………………………………………………..54
2.4.1 Port order connections……………………………………………………………………………55
2.4.2 Named port connections…………………………………………………………………………56
2.4.3 The dot-name inferred named port connection shortcut………………………………57
2.4.4 The dot-star inferred named port connection shortcut…………………………………58
2.5 Summary …………………………………………………………………………………………………………59
Chapter 3: Net and Variable types…………………………………………………………………61
3.1 Four-state data values………………………………………………………………………………………..61
3.2 Literal values (numbers)…………………………………………………………………………………….62
3.2.1 Literal integer values……………………………………………………………………………..62
3.2.2 Vector fill literal values………………………………………………………………………….65
3.2.3 Floating-point literal values (real numbers)……………………………………………….66
3.3 Types and data types …………………………………………………………………………………………66
3.3.1 Net types and variable types……………………………………………………………………66
3.3.2 Two-state and four-state data types (bit and logic)……………………………………..67
3.4 Variable types…………………………………………………………………………………………………..67
3.4.1 Synthesizable variable data types……………………………………………………………..67
3.4.2 Variable declaration rules……………………………………………………………………….70
3.4.3 Variable assignment rules……………………………………………………………………….74
3.4.4 Uninitialized variables……………………………………………………………………………74
3.4.5 In-line variable initialization……………………………………………………………………75
3.5 Net types………………………………………………………………………………………………………….76
3.5.1 Synthesizable net types…………………………………………………………………………..77
3.5.2 Net declaration rules………………………………………………………………………………79
Table of Contents XI
3.5.3 Implicit net declarations………………………………………………………………………….80
3.5.4 Net assignment and connection rules………………………………………………………..83
3.6 Port declarations ……………………………………………………………………………………………….84
3.6.1 Synthesizable port declarations………………………………………………………………..84
3.6.2 Non synthesizable port declarations…………………………………………………………87
3.6.3 Module port declaration recommendations……………………………………………….88
3.7 Unpacked arrays of nets and variables …………………………………………………………………89
3.7.1 Accessing array elements………………………………………………………………………..90
3.7.2 Copying arrays………………………………………………………………………………………91
3.7.3 Array list assignments…………………………………………………………………………….91
3.7.4 Bit-select and part-select of array elements……………………………………………….92
3.8 Parameter constants…………………………………………………………………………………………..93
3.8.1 Parameter dec larations……………………………………………………………………………94
3.8.2 Parameter overrides (parameter redefinition)…………………………………………….97
3.9 Const variables …………………………………………………………………………………………………99
3.10 Summary …………………………………………………………………………………………………………99
Chapter 4: User-defined Types and Packages……………………………………………….101
4.1 User-defined types……………………………………………………………………………………………101
4.1.1 Naming conventions for user-defined types…………………………………………….102
4.1.2 Local typedef definitions………………………………………………………………………..102
4.1.3 Shared typedef definitions…………………………………………………………………….102
4.2 SystemVerilog packages …………………………………………………………………………………..102
4.2.1 Package declarations……………………………………………………………………………..103
4.2.2 Using package items……………………………………………………………………………..104
4.2.3 Importing from multiple packages………………………………………………………….108
4.2.4 Package chaining………………………………………………………………………………….109
4.2.5 Package compilation order…………………………………………………………………….110
4.2.6 Synthesis considerations………………………………………………………………………..111
4.3 The $unit declaration space………………………………………………………………………………112
4.4 Enumerated types …………………………………………………………………………………………….114
4.4.1 Enumerated type declaration syntax………………………………………………………..114
4.4.2 Importing enumerated types from packages…………………………………………….117
4.4.3 Enumerated type assignment rules…………………………………………………………118
4.4.4 Enumerated type methods……………………………………………………………………..121
4.4.5 Traditional Verilog coding style without enumerated types……………………….124
4.5 Structures………………………………………………………………………………………………………..124
4.5.1 Structure declarations…………………………………………………………………………..124
4.5.2 Assigning to structure members…………………………………………………………….125
4.5.3 Assigning to entire structures…………………………………………………………………125
4.5.4 Typed and anonymous structures…………………………………………………………..126
4.5.5 Copying structures………………………………………………………………………………..127
4.5.6 Packed and unpacked structures…………………………………………………………….127
4.5.7 Passing structures through ports and to tasks and functions………………………..129
4.5.8 Traditional Verilog versus structures………………………………………………………130
4.5.9 Synthesis considerations……………………………………………………………………….130
4.6 Unions ……………………………………………………………………………………………………………131
4.6.1 Typed and anonymous unions……………………………………………………………….131
4.6.2 Assigning to, and reading from, union variables………………………………………132
4.6.3 Unpacked, packed and tagged unions……………………………………………………..132
4.6.4 Passing unions through ports and to tasks and functions……………………………134
4.7 Using arrays with structures and unions………………………………………………………………136
4.8 Summary ………………………………………………………………………………………………………..139
Chapter 5: RTL Expression Operators………………………………………………………..141
5.1 Operator expression rules………………………………………………………………………………….141
5.1.1 4-state and 2-state operations………………………………………………………………….142
5.1.2 X-optimism and X-pessimism………………………………………………………………142
5.1.3 Expression vector sizes and automatic vector extension……………………………144
5.1.4 Signed and unsigned expressions…………………………………………………………..145
5.1.5 Integer (vector) and real (floating-point) expressions……………………………….145
5.2 Concatenate and replicate operators……………………………………………………………………146
5.3 Conditional (ternary) operator……………………………………………………………………………150
5.4 Bitwise operators……………………………………………………………………………………………..153
5.5 Reduction operators………………………………………………………………………………………….158
5.6 Logical operators……………………………………………………………………………………………..160
5.6.1 Difference between negate and invert operations……………………………………..161
5.6.2 Short circuiting logical operations………………………………………………………….163
5.6.3 Non-synthesizable logical operators……………………………………………………….164
5.7 Comparison operators (equality and relational) …………………………………………………..164
5.8 Case equality (identity) operators……………………………………………………………………….168
5.9 Set membership (inside) operator……………………………………………………………………..171
5.10 Shift operators …………………………………………………………………………………………………173
5.10.1 Synthesizing shift operations………………………………………………………………….174
5.10.2 Synthesizing rotate operations………………………………………………………………177
5.11 Streaming operators (pack and unpack) ………………………………………………………………181
5.12 Arithmetic operators…………………………………………………………………………………………184
5.12.1 Integer and floating-point arithmetic………………………………………………………186
5.12.2 Unsigned and signed arithmetic might synthesize to the same gates…………..188
5.13 Increment and decrement operators ……………………………………………………………………189
5.13.1 Proper usage of increment and decrement operators…………………………………190
5.13.2 An example of correct usage of increment and decrement operators…………..192
5.13.3 Compound operations with increment and decrement operators…………………194
5.13.4 An anecdotal story on the increment and decrement operators………………….195
5.14 Assignment operators ……………………………………………………………………………………….196
5.15 Cast operators and type conversions ………………………………………………………………….198
5.15.1 Typecasting………………………………………………………………………………………..200
5.15.2 Size casting…………………………………………………………………………………………202
5.15.3 Signedness casting……………………………………………………………………………….206
Table of Contents XIII
5.16 Operator precedence………………………………………………………………………………………..209
5.17 Summary ……………………………………………………………………………………………………….210
Chapter 6: RTL Programming Statements…………………………………………………..211
6.1 SystemVerilog procedural blocks……………………………………………………………………….211
6.1.1 Sensitivity lists…………………………………………………………………………………….212
6.1.2 Begin-end statement groups……………………………………………………………………214
6.1.3 Using variables and nets in procedural blocks…………………………………………..216
6.2 Decision statements…………………………………………………………………………………………216
6.2.1 if-else statements………………………………………………………………………………….216
6.2.2 Case statements……………………………………………………………………………………222
6.2.3 Unique and priority decision modifiers…………………………………………………..227
6.3 Looping statements………………………………………………………………………………………….228
6.3.1 For loops…………………………………………………………………………………………….228
6.3.2 Repeat loops………………………………………………………………………………………..233
6.3.3 While and do-while loops……………………………………………………………………..235
6.3.4 Foreach loops and looping through arrays……………………………………………….236
6.4 Jump statements ……………………………………………………………………………………………..238
6.4.1 The continue and break jump statements…………………………………………………239
6.4.2 The disable jump statement…………………………………………………………………..240
6.5 No-op statement ……………………………………………………………………………………………..241
6.6 Functions and tasks in RTL modeling………………………………………………………………..243
6.6.1 Functions…………………………………………………………………………………………….243
6.6.2 Tasks………………………………………………………………………………………………….248
6.7 Summary ……………………………………………………………………………………………………….249
Chapter 7: Modeling Combinational Logic…………………………………………………..251
7.1 Continuous assignments (Boolean expressions) ………………………………………………….252
7.1.1 Explicit and inferred continuous assignments………………………………………….254
7.1.2 Multiple continuous assignments…………………………………………………………….254
7.1.3 Using both continuous assignments and always procedures……………………….255
7.2 The always and always_comb procedures ………………………………………………………….256
7.2.1 Synthesizing combinational logic always procedures……………………………….257
7.2.2 Modeling with the general purpose always procedure………………………………257
7.2.3 Modeling with the RTL-specific always_comb procedure…………………………260
7.2.4 Using blocking (combinational logic) assignments…………………………………..261
7.2.5 Avoiding unintentional latches in combinational logic procedures……………..262
7.3 Using functions to represent combinational logic………………………………………………..263
7.4 Combinational logic decision priority………………………………………………………………..265
7.4.1 Removing unnecessary priority encoding from case decisions……………………266
7.4.2 The unique and uniqueO decision modifiers…………………………………………….266
7.4.3 The obsolete parallel_case synthesis pragma…………………………………………..270
7.5 Summary ……………………………………………………………………………………………………….271
xiv RTL Modeling with SystemVerilog for Simulation and Synthesis
Chapter 8: Modeling Sequential Logic………………………………………………………….273
8.1 RTL models of flip-flops and registers ………………………………………………………………274
8.1.1 Synthesis requirements for RTL sequential logic……………………………………..274
8.1.2 Always procedures and always_ff procedures…………………………………………..275
8.1.3 Sequential logic clock-to-Q propagation and setup/hold times……………………276
8.1.4 Using nonblocking (sequential logic) assignments……………………………………278
8.1.5 Synchronous and asynchronous resets…………………………………………………….286
8.1.6 Multiple clocks and clock domain crossing (CDC)……………………………………295
8.1.7 Additional RTL sequential logic modeling considerations…………………………297
8.2 Modeling Finite State Machines (FSMs) ……………………………………………………………299
8.2.1 Mealy and Moore FSM architectures………………………………………………………301
8.2.2 State encoding……………………………………………………………………………………..302
8.2.3 One, two and three-procedure FSM coding styles…………………………………….305
8.2.4 A complete FSM example…………………………………………………………………….309
8.2.5 Reverse case statement one-hot decoder…………………………………………………313
8.2.6 Avoiding latches in state machine decoders…………………………………………….317
8.3 Modeling memory devices such as RAMs………………………………………………………….317
8.3.1 Modeling asynchronous and synchronous memory devices……………………….319
8.3.2 Loading memory models using Sreadmemb and Sreadmemh…………………….320
8.4 Summary ……………………………………………………………………………………………………….322
Chapter 9: Modeling Latches and Avoiding Unintentional Latches……………..323
9.1 Modeling Latches ……………………………………………………………………………………………323
9.1.1 Modeling latches with the general purpose always procedure……………………324
9.1.2 Modeling latches with the always_latch procedure…………………………………..325
9.2 Unintentional latch inference ……………………………………………………………………………327
9.3 Avoiding latches in intentionally incomplete decisions………………………………………..329
9.3.1 Latch avoidance coding style trade-offs………………………………………………….330
9.3.2 A small example to illustrate avoiding unintentional latches……………………..332
9.3.3 Latch avoidance style 1 — Default case item with known values………………335
9.3.4 Latch avoidance style 2—Pre-case assignment, known values…………………..338
9.3.5 Latch avoidance style 3 — unique and priority decision modifiers…………….340
9.3.6 Latch avoidance style 4 — X assignments for unused decision values………..345
9.3.7 Latch avoidance style 5 — the full_case synthesis pragma………………………..350
9.3.8 Additional notes about synthesis pragmas……………………………………………….351
9.4 Summary ……………………………………………………………………………………………………….353
Chapter 10: Modeling Communication Buses — Interface Ports……………….355
10.1 Interface port concepts …………………………………………………………………………………….356
10.1.1 Traditional Verilog bus connections……………………………………………………….357
10.1.2 SystemVerilog interface definitions……………………………………………………….361
10.1.3 Referencing signals within an interface…………………………………………………..365
10.1.4 Differences between modules and interfaces…………………………………………….365
10.1.5 Source code declaration order………………………………………………………………..366
10.2 Using interfaces as module ports……………………………………………………………………….366
Table of Contents xv
10.2.1 Generic interface ports………………………………………………………………………….366
10.2.2 Type-specific interface ports…………………………………………………………………367
10.3 Interface modports…………………………………………………………………………………………..367
10.3.1 Specifying which modport view to use…………………………………………………..368
10.3.2 Using modports to define different sets of connections…………………………….371
10.4 Interface methods (tasks and functions)……………………………………………………………..372
10.4.1 Calling methods defined in an interface………………………………………………….374
10.4.2 Synthesizing interface methods……………………………………………………………..375
10.4.3 Abstract, non-synthesizable interface methods………………………………………..375
10.5 Interface procedural code …………………………………………………………………………………376
10.6 Parameterized interfaces…………………………………………………………………………………..378
10.7 Synthesizing interfaces…………………………………………………………………………………….379
10.8 Summary ……………………………………………………………………………………………………….382
List of Appendices…………………………………………………………………………………………383
Appendix A: Best Practice Coding Guidelines…………………………………………….385
Appendix B: SystemVerilog Reserved Keywords………………………………………..391
B.l All SystemVerilog-2012 reserved keywords………………………………………………………391
B.2 Verilog-1995 reserved keywords ……………………………………………………………………..393
B.3 Verilog-2001 reserved keywords ……………………………………………………………………..394
B.4 Verilog-2005 reserved keywords ……………………………………………………………………..394
B.5 System Verilog-2005 reserved keywords…………………………………………………………….395
B.6 SystemVerilog-2009 reserved keywords…………………………………………………………….396
B.7 SystemVerilog-2012 reserved keywords…………………………………………………………….396
B. 8 SystemVerilog-2017 reserved keywords…………………………………………………………….396
Appendix C: X Optimism and X Pessimism in RTL Models……………………….397
C. 1 Introducing My X……………………………………………………………………………………………398
C.2 How did my one (or zero) become my X? ………………………………………………………….399
C.2.1 Uninitialized 4-state variables………………………………………………………………399
C.2.2 Uninitialized registers and latches…………………………………………………………400
C.2.3 Low power logic shutdown or power-up………………………………………………..401
C.2.4 Unconnected module input ports…………………………………………………………..401
C.2.5 Multi-driver Conflicts (Bus Contention)………………………………………………..401
C.2.6 Operations with an unknown result……………………………………………………….401
C.2.7 Out-of-range bit-selects and array indices………………………………………………401
C.2.8 Logic gates with unknown output values……………………………………………….402
C.2.9 Setup or hold timing violations……………………………………………………………..402
C.2.10 User-assigned X values in hardware models……………………………………………402
C.2.11 Testbench X injection………………………………………………………………………….403
xvi RTL Modeling with SystemVerilog for Simulation and Synthesis
C.3 An optimistic X — is that good or bad?…………………………………………………………….403
C.3.1 If…else statements……………………………………………………………………………….404
C.3.2 Case statements without a default-X assignment…………………………………….407
C.3.3 Casex, casez and case…inside statements……………………………………………….408
C.3.4 Bitwise, unary reduction, and logical operators………………………………………411
C.3.5 And, nand, or, nor, logic primitives……………………………………………………….412
C.3.6 User-defined primitives……………………………………………………………………….412
C.3.7 Array index with X or Z bits for write operations……………………………………412
C.3.8 Net data types……………………………………………………………………………………..413
C.3.9 Posedge and negedge edge sensitivity……………………………………………………414
C.4 A pessimistic X — is that any better? ……………………………………………………………….415
C.4.1 If…else statements with X assignments………………………………………………….416
C.4.2 Conditional operator……………………………………………………………………………417
C.4.3 Case statements with X assignments……………………………………………………..419
C.4.4 Edge-sensitive X pessimism…………………………………………………………………420
C.4.5 Bitwise, unary reduction, and logical operators………………………………………420
C.4.6 Equality, relational, and arithmetic operators………………………………………….421
C.4.7 User-defined primitives……………………………………………………………………….422
C.4.8 Bit-select, part-select, array index on right-hand side of assignments………..423
C.4.9 Shift operations…………………………………………………………………………………..423
C.4.10 X-pessimism summary………………………………………………………………………..424
C.5 Eliminating my X by using 2-state simulation……………………………………………………424
C.6 Eliminating some of my X with 2-state data types ……………………………………………..426
C.7 Breaking the rules—simulator-specific X-propagation options…………………………….428
C.8 Changing the rules — A SystemVerilog enhancement wish list …………………………..429
C.9 Detecting and stopping my X at the door…………………………………………………………..430
C. 10 Minimizing problems with my X ……………………………………………………………………..432
C. 10.1 2-state versus 4-state guidelines……………………………………………………………432
C.10.2 Register initialization guidelines…………………………………………………………..433
C.10.3 X-assignment guidelines………………………………………………………………………433
C.10.4 Trapping X guidelines…………………………………………………………………………433
C.ll Conclusions …………………………………………………………………………………………………..434
C. 11.1 About the author…………………………………………………………………………………435
C.12 Acknowledgments ………………………………………………………………………………………….435
C.13 References …………………………………………………………………………………………………….436
Appendix D: Additional Resources………………………………………………………………437
Index
Stuart Sutherland provides expert SystemVerilog training workshops and consulting services. Stuart has more than 30 years of experience with Verilog and SystemVerilog. He has served as the technical editor for every version of the IEEE Verilog and SystemVerilog Language Reference Manuals (LRMs). Stuart founded Sutherland HDL, Inc. in 1992, located in Tualatin, Oregon, USA. Stuart has authored and co-authored numerous papers on these languages (available at www.sutherland-hdl.com). He has authored the books: “The Verilog PLI Handbook”,”Verilog-2001: A Guide to the New Features of the Verilog HDL, and “SystemVerilog for Design: A Guide to Using the SystemVerilog Enhancements to Verilog for Hardware Design” (co-authored with Simon Davidmann and Peter Flake), and “Verilog and SystemVerilog Gotchas:101 Common Coding Error and How to Avoid Them” (co-authored with Don Mills)”. Stuart holds a Bachelor’s Degree in Computer Science with an emphasis in Electronic Engineering Technology from Weber State University (Ogden, Utah) and Franklin Pierce College (Nashua, New Hampshire), and a Master’s Degree in Education with an emphasis on eLearning course development from Northcentral University (Prescott, Arizona).
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